Circuits And Systems Exploration (CASE) Lab

School of Engineering and Technology, Central Michigan University, Mt Pleasant, MI

 

Projects

PDF documents for paper published are available in the Publication page here


Object Localization using Portable Sensor Networks

                                                                                                       This project is funded by the CMU- Office of Research and Sponsored Programs.

 

More information coming soon ...


  1. BulletA. Ghelichi, K. Yelamarthi, A. Abdelgawad, “Target Localization in Wireless Sensor Network Based on Time Difference of Arrival,” IEEE International Midwest Symposium on Circuits and Systems, Aug 2013.

  2. BulletB. Olszewski, S. Fenton, B. Tworek, J. Liang, K. Yelamarthi, “RFID Positioning Robot: An Indoor Navigation System,” IEEE International Conference on Electro/Information Technology, May 2013.




Autonomous Mobile Tour-Guide Robot

   Everyday numerous students and their families visit CMU’s campus each year to decide if it is the right school for them. However, in the limited time available during a campus tour, it is difficult for them to develop a good understanding of the engineering and technology (ET) programs offered at CMU. This research is primarily focused on the design of a Autonomous Mobile Tour-Guide Robot (AMTGR). Utilizing RFID tags for location identification, and ultrasonic sensors for obstacle detection, the AMTGR provides the CMU visitors with up-to date information on ET programs and research conducted at CMU.

                           This project is funded in-part by the CMU-College of Science & Technology, Office of Research and Sponsored Programs.

  1. BulletK. Yelamarthi, S. Sherbrook, J. Beckwith, M. Williams, R. Lefief, “An RFID based Semi-Autonomous Indoor Tour Guide Robot,” IEEE International Midwest Symposium on Circuits and Systems, August 2012.

  2. BulletK. Yelamarthi, “Tour Guide Robot: A Platform for Interdisciplinary Engineering Senior Design Projects,” 119th Annual ASEE Conference & Exposition, June 2012.

  3. BulletJ. Beckwith, S. Sherbrook, R. Lefief, M. Williams, K. Yelamarthi, “CATE: An Indoor Tour Guide Robot,” IEEE International Conference on Electro/Information Technology, May 2012.

  4. BulletJ. Beckwith, S. Sherbrook, R. Lefief, M. Williams, K. Yelamarthi, “Central Automated Tour Experience (CATE) – An Interdisciplinary Senior Design Project,” ASEE North Central Section Conference, March 2012

  5. BulletJ. Mitchell, A. Adkins, N. Trela, K. Yelamarthi, “Tour Guide Robot: An Electrical Engineering Capstone Senior Design Project,” 2011 ASEE North Central and Illinois-India Section Conference, April 2011




Performance Optimization of Nano-scale CMOS Circuits

    The advancement of semiconductor technology with the shrinking device, currently at 45 nanometers has allowed for placement of billions of transistor on a single microprocessor chip. At the same time, the extremely low gate delays and shrinking device sizes has presented the design engineers with two major challenges: 1) timing optimization at multiple giga-hertz frequencies, and 2) reducing the daunting effects of semiconductor process variations. Failure to account for these process variations often results in loss of design productivity by one generation, and might even result in catastrophic design failure.


    This research presents a just-in-time timing optimization approach that partitions a design, chooses efficient circuit style (static or dynamic) for each partition, and performs timing optimization while accounting for process variations. The presented algorithm can be used as a tape-out rescue mechanism from timing failure, for timing optimization, and can be easily incorporated into many of the optimization flows currently used by the industry.


  1. BulletK. Yelamarthi, “Timing-Driven Variation-Aware Partitioning and Optimization of Mixed Static-Dynamic CMOS Circuits,” Journal of Circuits and Systems, May 2013.

  2. BulletK. Yelamarthi, C-I. H. Chen, “Timing Optimization and Noise Tolerance for Dynamic CMOS Susceptible to Process Variations,” IEEE Transactions on Semiconductor Manufacturing, vol. 25, no. 2, pp. 255-265, May 2012.

  3. BulletK. Yelamarthi, C-I. Chen, “A Timing Optimization Technique for Nanoscale CMOS Circuits Susceptible to Variations,” IEEE International Instrumentation and Measurement Technology Conference, May 2011.

  4. BulletK. Yelamarthi, C-I.H. Chen, “A Delay and Performance Optimization Algorithm for Dynamic CMOS Circuits,” IEEE International Symposium on Quality Electronic Design, Mar 2011.

  5. BulletK. Yelamarthi, C-I.H. Chen, “ Dynamic CMOS Load Balance and Path Oriented in Time Optimization to Minimized Delay Uncertainties from Process Variations,” VLSI Design, 2010.

  6. BulletK. Yelamarthi, C-I. H. Chen, “Process Variation-Aware Timing Optimization for Dynamic and Mixed-Static-Dynamic CMOS Logic,” IEEE Transaction on Semiconductor Manufacturing, vol. 22, no.1, pp.31-39, Feb 2009.

  7. BulletK. Yelamarthi and C-I. H. Chen, “A Path Oriented In Time Optimization Flow for Mixed-Static-Dynamic CMOS Logic,” IEEE Midwest Circuits and Systems Conference, Aug 2008.






Assistive Technology

   For people with vision disabilities, it has always been difficult to accomplish many day-to-day activities. Identifying different buildings and finding the best route to reach a location is one of the difficult tasks for a person with limited or no sight capabilities. Technological advancement such as Radio Frequency Identification (RFID) is the answer for this and many other challenges for people with vision impairments. This research is primarily focused on the design of smart-devices for the blind. Utilizing RFID tags for location identification, and ultrasonics for obstacle detection, the smart-device helps the blind to safely navigate in a predefined location.

This project is funded in-part by the CMU-Office of Research and Sponsored Programs.

  1. BulletK. Yelamarthi, “RFID-Based Interdisciplinary Educational Platform to Improve the Engineering and Technology Curriculums,” Journal of STEM Education: Innovations and Research, vol. 13, no.5, pp.46-51, Dec 2012.

  2. BulletK. Yelamarthi, D. Haas, D. Nielsen, S. Mothersell, “RFID and GPS Integrated Navigation System for the Visually Impaired,” IEEE International Midwest Symposium on Circuits and Systems, August 2010.

  3. BulletK. Yelamarthi, P. R. Mawasha “RFID based Assistive Devices: An Interdisciplinary Platform for Senior Design Projects in Engineering Disciplines,” Annual ASEE Conference & Exposition, June 2010.

  4. BulletD. Haas, S. Mothersell, D. Nielsen, K. Yelamarthi, “A Smart Robot for the Visually Impaired,” ASEE North Central Section Conference, March 2010.

  5. BulletW. Martin, K. Dancer, K. Rock, C. Zeleny, K. Yelamarthi, “The Smart Cane: An Electrical Engineering Design Project,” ASEE North Central Section Conference, April 2009.